(1) Field of the Invention
This invention relates to a method used to fabricate a semiconductor device, and more specifically to a method used to form a high surface area capacitor structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
The use of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed DRAM device densities to reach 256 MByte, and beyond. However as the dimension of critical DRAM features are reduced, to accommodate desired densities, difficulties in achieving critical DRAM parameters, such as capacitance, have arisen. For example DRAM cells, using stacked capacitor configurations, are limited by the dimensions of the underlying transfer gate transistor. The capacitance supplied by the stacked capacitor structure, of the DRAM device, is a function of the thickness of capacitor dielectric layer, as well as a function of the area of the capacitor. Since the amount of thickness reduction of the the capacitor dielectric layer is reliability, as well as yield, limited efforts have been directed at increasing DRAM capacitance by increasing capacitor area, while still restricted by the reduced dimensions of the underlying transfer gate transistors.
One method of increasing capacitor surface area, without increasing the dimensions of a stacked capacitor structure, has been the use of hemispherical grained, (HSG), silicon layers, used as a top surface layer for a storage node electrode structure. The HSG silicon layer offers a layer with a series of concave and convex features, thus increasing surface area, and thus capacitance, for the stacked capacitor structure. For example Lou, in U.S. Pat. No. 5,618,747, describes a detailed process for forming a stacked capacitor structure, incorporating an HSG silicon layer. However the use of higher dielectric constant layers, such as barium strontium titanate, (BST), lead zirconate titanate, (PZT), as well as tantalum oxide, offering increased capacitance using thicknesses equal to other materials such as silicon oxide, are more compatible interfacing electrode materials comprised of titanium nitride, (TiN), then silicon materials.
This invention will describe a process for forming capacitor structures using TiN as part of the capacitor structure, and in addition will offer a process in which HSG TiN layer is formed, thus offering increased surface area, and thus increased capacitance, when compared to counterparts fabricated with smooth TiN layers. Prior art, such as Harshfield, in U.S. Pat. No. 5,612,558, describe a method for forming HSG silicon, using an underlying seed layer of TiN, however that prior art does not use HSG TiN for the surface layer of a storage node electrode structure.